1. Field of the Invention
The area of the present invention relates generally to programmable logic devices and, more particularly, to programmable logic devices having a data conversion capability.
2. Background Art
In data communication and telecommunication applications the need to convert data from parallel data words to a serial data stream or from a serial data stream to parallel data is a frequent requirement. In Complex Programmable Logic Devices (CPLDs) and Filed Programmable Gate Arrays (FPGs) used in these applications this conversion is accomplished by use of logic block or logic cell register resources. When FPGA logic cell registers, or CPLD macrocell registers, are used strictly as shift register stages, the logic associated with the registers so employed is typically wasted.
Occasionally, a small amount of RAM (a few bytes) is needed in a design implemented in an FPGA or CPLD. In other than Look-Up-Table RAM based FPGAs, precious logic cell registers or CPLD macrocell registers may be used to implement this RAM. Typically, the logic resources associated with these registers is, again, wasted,
The result of using the registers of FPGA logic cells or CPLD macrocells to create the structures required to perform serial-to-parallel and parallel-to-serial data conversion is inefficient use of the limited register resources. This very low logic efficiency means that a greater number of components is required and greater board area than would otherwise be necessary is used.